This invention relates generally to testing of integrated circuits, and more specifically, to testing of memories on integrated circuits.
Memory built-in self-test (BIST) circuitry is commonly found on integrated circuits having embedded memory for the purpose of verifying that the embedded memory may be written and/or read properly over the life of the integrated circuits. In such forms, the embedded memory is dynamic random access memory (DRAM) or static random access memory (SRAM) as there are known fixed test algorithms which may commonly be used for various circuit and process implementations of volatile memory. Users of such integrated circuits are typically unaware of the BIST circuitry which functions primarily as a manufacturing test mechanism. For this reason and others, there is a desire to minimize the amount of die area that is used for the BIST function.
Integrated circuits are commonly using embedded memories that are non-volatile. These non-volatile memories, other than Read-Only Memories (ROMs), are generally more complex to test than volatile memories. For example, non-volatile memories are implemented with various memory cell circuit designs and using different processing technologies. Additionally, some circuit designs have embedded memory arrays using different non-volatile memory types, such as flash (bulk erased) or electrically erasable (byte/word erasable). Different erasing, programming, read and stress algorithms are required for each different type of non-volatile memory. Such integrated circuits as a result generally have not implemented built-in self-test controllers. When testing of integrated circuits having non-volatile memory arrays is performed, increased test time and cost is typical because of the increased test complexity as compared with the testing of embedded volatile memories.